1. Field of the Invention
The present invention relates generally to communications networks and more particularly to Local Area Networks (LANs) or similar networks using ethernet and/or CSMA/CD (Carrier Sense Multiple Access with Collision Detect) protocols.
2. Prior Art
Ethernet and IEEE 802.3 LANs, among others, have become increasingly popular as the network of choice for interconnecting electrical machines such as computers, word processors, servers, switches, etc. Both the ethernet and IEEE 802.3 LANs are collision type networks in which a single and/or plural stations are connected to a common media. Access to the common media is controlled by the protocol.
Broadly speaking, any station may be analyzed in terms of the ISO model. This model has eight layers, with the media and structure for coupling the device to the media being classified in the two lower layers (i.e., Physical [PHY] and LLC) of the eight layer model. The other six layers are used to describe the device. The structure used to couple devices to the media is referred to as Network Interface Card (NIC) adapters or similar names. The protocols, such as ethernet and/or IEEE 802.3, for accessing the network, are provided in the NIC.
As the popularity of LANs grows, more and more demands are placed on them. The demands require improvement on old functions and providing new ones. One of the areas of demand for improved function is media speed. Historically, the standard speed for an ethernet LAN was 10 Mbps. However, ethernet has migrated from 10 Mbps to 100 Mbps and onto Gigabit ethernet (1000 Mbps). The demand for new function includes ACPI Power Management, IEEE 802.3X Flow Control, and Wake On LAN.
Several prior art references describe NICs for coupling devices to ethernet LANs. However, none of the references describe a comprehensive architecture, for a NIC, that provides both low and high speed data transmission and provide new functions. Examples of prior art include the following:
U.S. Pat. No. 5,311,509 describes a transmission system including a transmitter section, a switching module and a receiver section. The transmitter section transforms frames of user data in fixed ATM cells which are transported through the switching module and re-assembled into frames of user data by the receiver section.
U.S. Pat. No. 5,404,544 describes a Media Access Controller (MAC) for coupling devices to a 10 Base-T ethernet LAN. Usually, the 10 Base-T ethernet LAN is a relatively low speed (10 Mbps) network.
U.S. Pat. Nos. 5,412,782 and 5,485,584 describe a minimal latency adapter in which the adapter initiates an early interrupt for DMA transfer with the host prior to receiving a complete packet from the network. Data transfer from the network to the adapter overlap with data transfer from the adapter to the host.
U.S. Pat. No. 5,446,914 describes a coding and transceiving ethernet circuit that connects an external controller to twisted pair or coax cabling system.
U.S. Pat. No. 5,526,355 describes a modified ethernet protocol with short and long interpacket gaps (IPG). The station winning access to the media after a collision uses the short IPG between data packets. The losing station uses the long IPG before it attempts to gain access to the media. The use of the long and short IPGs is alternated between the stations.
U.S. Pat. No. 5,596,575 describes a 10 Mbps/100 Mbps adapter that automatically adjusts to the speed of the network.
U.S. Pat. No. 5,642,360 describes algorithms for adjusting Inter Frame Spacing (IFS) used by an ethernet controller to regulate data throughput.
It is an object of the present invention to provide the architecture for a NIC that supports data speeds of 10 Mbps, 100 Mbps and 1000 Mbps (Gigabits).
It is another object of the present invention to provide the architecture for a NIC that embraces new functions including ACPI (Advanced Configuration and Power Interface) Power Management, IEEE 802.3X Flow Control and Wake-On-LAN.
The NIC that embodies the architecture includes a Master and Slave host bus interface with block size control registers, a microprocessor controller, transmit (TX) storage, Local Storage, Receive (Rx) storage, ethernet MAC (EMAC) layer control hardware, and hardware assist logic coupling the microprocessor controller to the named structures. The block size for data is set in the block size control registers. The microprocessor controller uses the block size information and information stored in the host buffer descriptors to control the flow of data through the NIC. The efficiency of the NIC is further enhanced by the microprocessor initiating and causing several operations (discussed below) to be executed simultaneously.
Other features of the NIC include multiple queued transmit frames, control word per data block, programmable interframe gap timer, priority queues, Wake-On-LAN, debug interface, prefetch buffer descriptor for receive operation, hardware assists for building addresses, and microprocessor controller IPL from EEPROM.